1. Field of the Invention
The present invention relates to a method of fabricating an insulated gate semiconductor device such as an MOSFET, for example, and more particularly, it relates to an improvement for preventing an etch-down phenomenon in a gate electrode.
2. Background of the Invention
An insulated gate semiconductor device has such a structure that p-type and n-type semiconductor layers are alternately connected with each other so that main electrodes which are fed with a main current are connected to endmost semiconductor layers and a gate electrode for forming a channel by application of an electric field is connected to at least one semiconductor layer through an insulating film. In this insulated gate semiconductor device, the main current flowing across the two main electrodes is controlled by a voltage which is applied to the gate electrode. Typical examples of such a semiconductor device are a MOSFET (MOS field effect transistor) and an IGBT (insulated gate bipolar transistor).
In the insulated gate semiconductor device, a number of elements having the same structure (hereinafter referred to as unit cells) are generally connected in parallel with each other. Such a structure is particularly preferable in a power insulated gate semiconductor device.
FIG. 37 is a plan view typically showing a part of a MOSFET 50 which is known in general, and FIG. 38 is a sectional view taken along the line X--X in FIG. 37. In this MOSFET 50, a number of unit cells are arranged on both sides of a gate wire 9 in the form of a matrix. FIGS. 37 and 38 illustrate the gate wire 9 and the unit cells which are adjacent thereto.
In this MOSFET 50, an n.sup.- -type semiconductor layer 2 containing an n-type impurity of low concentration is formed on a semiconductor substrate structuring an n.sup.+ -type semiconductor layer 1 containing an n-type impurity in high concentration, while p base layers 3 and a p well 3a are selectively formed by selectively diffusing a p-type impurity in an upper major surface portion of the n.sup.- -type semiconductor layer 2. The p base layers 3 are formed for the respective unit cells, while the p well 3a is formed immediately under the gate wire 9.
Further, n.sup.+ emitter layers 4 are selectively formed on upper major surfaces of the p base layers 3 by selectively diffusing an n-type impurity of high concentration. A flat plate type semiconductor substrate 60 is formed by these five types of semiconductor layers. A gate electrode 6 consisting of polysilicon is arranged on an upper major surface of the semiconductor substrate 60 consisting of silicon, through a gate insulating film 5 which is formed by a silicon oxide film. FIG. 37 shows the gate electrode 6 in a hatched manner.
The gate electrode 6 is provided with an opening (gate opening) 13 every unit cell, so that its opening edge is positioned immediately above the outer edge of each n.sup.+ emitter layer 4 or somewhat inwardly. Namely, the gate electrode 6 is so arranged as to cover an upper surface portion of each p base layer 3 which is held between each n.sup.+ emitter layer 4 and the n.sup.- semiconductor layer 2, i.e., a channel region 61, in each unit cell.
The gate electrode 6 is covered with a protective film 7 which is formed by a silicon oxide film. This protective film 7 is provided with openings 13 inside the gate openings 13. Source electrodes 8 are connected to upper surfaces of the n.sup.+ emitter layers 4 and those of the p base layers 3 held between the n.sup.+ emitter layers 4 for the respective unit cells. The source electrodes 8 are electrically insulated from the gate electrode 6 by the protective film 7.
The protective film 7 is further provided with an opening 11 in a position corresponding to that immediately above the p well 3a. The aforementioned gate wire 9 is connected to the gate electrode 6 through the opening 11. This gate wire 9 is electrically insulated from the source electrodes 8. Both of the source electrodes 8 and the gate wire 9 are made of conductive Al-Si (solid solution of aluminum and silicon). A drain electrode 10 consisting of conductive Ti/Ni/Au (alloy containing titanium, nickel and gold) is formed on a lower major surface of the semiconductor substrate 60, i.e., that of the n.sup.+ -type semiconductor layer 1.
In order to use this MOSFET 50, a drain voltage V.sub.DS is first positively applied across the drain electrode 10 and the source electrodes 8, by connecting an external power source. In this state, a gate voltage V.sub.GS exceeding a prescribed gate threshold voltage V.sub.GS(th) is positively applied across the gate electrode 6 and the source electrodes 8 through the gate wire 9 (namely, the gate is turned on), so that the p-type channel regions 61 which are parts of the p base layers 3 are reversed to n types, whereby n-type channels are formed in the channel regions 61. The n.sup.+ emitter layers 4 and the n.sup.- -type semiconductor layer 2 conduct by these channels. Consequently, the main current flows from the drain electrode 10 to the source electrodes 8. Namely, the MOSFET 50 conducts.
Then, the gate voltage V.sub.GS is returned to a zero or minus (reverse bias) value (namely, the gate is turned off), so that the channels formed in the channel regions 61 disappear and the channel regions 61 are restored to the original p conductivity type. Consequently, the n.sup.+ emitter layers 4 are disconnected from the n.sup.- -type semiconductor layer 2, whereby no main current flows. Namely, the MOSFET 50 enters a nonconducting state.
This MOSFET 50 is generally fabricated in the following steps: Namely, the semiconductor substrate 60 is prepared so that the gate insulating film 5 and the gate electrode 6 are formed on the upper surface thereof, and thereafter the protective film 7 is temporarily formed to cover all these elements. Thereafter the openings 11 and 12 are simultaneously formed in the protective film 7 by photolithography. Then, an Al-Si layer is deposited by sputtering or vapor deposition to entirely cover the openings 11 and 12 and the protective film 7. Thereafter the Al-Si layer is selectively removed by photolithography, thereby forming the source electrodes 8 and the gate wire 9.
In the aforementioned conventional fabrication steps, the openings 11 and 12 are formed in the protective film 7 by dry etching. When the dry etching is employed, there is no possibility that the openings 12 are unnecessarily enlarged by side etching. Thus, it is possible to reliably ensure the insulation between the source electrodes 8 and the gate electrode 6, thereby attaining an effect of reducing the percentage defective of products resulting from defective insulation in these portions. This effect is particularly important when the unit cells are refined, and the importance is particularly increased when the widths of the openings 12 are not more than 0.8 .mu.m, for example.
As shown in a front sectional view of FIG. 39, further, it is possible to etch down the upper surface of the semiconductor substrate 60 to a proper depth (T in FIG. 39) in each opening 12 by employing dry etching. Thus, an action of extracting carriers remaining in the p base layer 3 appears and hence the speed (switching speed) in a switching operation is effectively increased. Further, another action of suppressing conduction of parasitic bipolar transistors which are unavoidably formed in the semiconductor substrate 60 so appears that it is possible to suppress breaking of the MOSFET 50 caused by a latch-up phenomenon.
Due to the employment of the dry etching, however, the conventional method of fabricating the MOSFET 50 has other problems.
First, the etching so excessively progresses in the opening 11 due to the employment of the dry etching that the gate electrode 6 may be unnecessarily etched down (in a portion S shown in FIG. 39). The gate electrode 6 is disadvantageously reduced in thickness due to such an unnecessary etch-down phenomenon, leading to retardation in switching speed of the MOSFET 50.
Second, the etch-down phenomenon in the opening 11 disadvantageously reaches the gate insulating film 5 to cause defective electrical insulation by the gate insulating film 5, leading to short-circuiting across the gate electrode 6 and the semiconductor substrate 60. Consequently, the percentage defective of the MOSFET 50 is disadvantageously increased by the defective insulation.